The present invention relates to switching circuits, and more particularly to a high speed current mode logic circuit.
In logic circuits the input and output can take on one of two values and the output reflects a predetermined logical relationship between the input and output of the circuit. When the output of a circuit has a value between the two logical values which it is designed to generate, the output is indeterminate and is not useful to other logic circuits which receive this output. Logic circuits within a network of logic circuits which receive an indeterminate input signal must delay producing an output signal until the input has reached a final value. This delay propagates from one circuit to another and can seriously degrade the performance of the logic network.
Often times, within logical networks, signals are sent which are imperfect in a variety of ways. Some signals may have glitches which are brief changes in a signal value which do not reflect a change from one logical value to the next. A glitch in the input can cause a corresponding change in state of the logical circuit receiving this input. An output responsive to the glitch will be in error.
Prior to the present invention, when an input takes a relatively long time to switch from one logical value to another, the output logic will be indeterminate for this transition time period. Hysteresis, i.e., delaying the change in the output until the input nearly reaches its next logical value at the end of the transition time period, reduces the period of time that the output value will be indeterminate.
Circuits which introduce hysteresis, such as Schmidt triggers, have been designed for a variety of circuit types and device constructions which include implementations in emitter-coupled bipolar logic, NMOS and CMOS technologies. Many versions of the Schmitt trigger are constructed from two inverters connected in series with the output of the first inverter fed positively to the second inverter to achieve hysteresis in the DC transfer curve.
In bipolar emitter coupled logic, hysteresis is achieved by a trigger circuit that changes a reference voltage in accordance with the output of a resistor voltage divider. This implementation becomes impractical as the load current of modern emitter coupled logic is shrunk to a fraction of a milliampere. In order to minimize DC current in the resistor voltage divider to a small fraction of the load current, resistors used in the resistor voltage divider network of a trigger, circuit such as a Schmitt trigger must exceed megaohms. Implanted resistors have too small resistivity to be used and thin film resistors tend to complicate processing.
For logic circuits implemented in galium arsenide technologies, particularly metal semiconductor field effect transistors (MESFET), the resistor voltage divider approach is particularly impractical because at the present time high resistivity thin film resistors are not available for most GaAs processing.
Additionally, in GaAs MESFET circuits there is fairly strict maximum DC current loading requirements for the reference voltage power supply which makes resistive networks difficult to work with. In addition for saturated current mode GaAs MESFET circuits, as described in U.S. patent application Ser. No. 06/725,255, half of the DC current passes through clamping diodes and the other half passes through a load MESFET. There is an even greater need to minimize any loss of DC current due to a trigger circuit such as a Schmitt trigger in these types of circuits.